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Integrated Circuit Systems, Inc.
ICS843002I-01
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FEMTOCLOCKSTM CRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
FEATURES
* Two 3.3V or 2.5V LVPECL outputs * Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input * Supports the following output frequencies: 156.25MHz, 125MHz and 62.5MHz * VCO range: 560MHz - 680MHz * RMS phase jitter @ 156.25MHz, using a 25MHz crystal (1.875MHz-20MHz): 0.55ps (typical) * Output skew: 30ps (maximum) * Supply Voltage Modes Core/Outputs 3.3/3.3 2.5/2.5 * -40C to 85C ambient operating temperature * Available in both standard and lead-free RoHS-compliant packages
GENERAL DESCRIPTION
The ICS843002I-01 is a 2 output LVPECL synthesizer optimized to generate Ethernet HiPerClockSTM reference clock frequencies and is a member of the HiPerClocks TM family of high performance clock solutions from ICS. Using a 25MHz 18pF parallel resonant crystal, the following frequencies can be generated based on the 2 frequency select pins (F_SEL[1:0]): 156.25MHz, 125MHz, and 62.5MHz. The ICS843002I-01 uses ICS' FemtoClock TM low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting Ethernet jitter requirements. The ICS843002I-01 is packaged in a small 20-pin TSSOP package.
IC S
FREQUENCY SELECT FUNCTION TABLE
Inputs M Divider F_SEL1 F_SEL0 Value 0 0 25 0 1 1 1 0 1 25 25 25 N Divider Value 4 5 10 5 Output Frequency (25MHz Ref.) 156.25 (default) 125 62.5 12 5
PIN ASSIGNMENT
nc VCCO Q0 nQ0 MR nPLL_SEL nc VCCA F_SEL0 VCC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCCO Q1 nQ1 VEE VCC nXTAL_SEL REF_CLK XTAL_IN XTAL_OUT F_SEL1
ICS843002I-01
BLOCK DIAGRAM
F_SEL[1:0] Pulldown nPLL_SEL Pulldown 2 F_SEL[1:0] 00 01 10 11 /4 (default) /5 /10 /5
20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm package body G Package Q0 Top View
nQ0
REF_CLK Pulldown
25MHz
1
1
Q1 nQ1
XTAL_IN XTAL_OUT
OSC
0
Phase Detector
VCO 625MHz
(w/25MHz Reference)
0
nXTAL_SEL Pulldown
M = 25 (fixed)
MR Pulldown
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FEMTOCLOCKSTM CRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
Type Description No connect. Output supply pins. Differential output pair. LVPECL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs nQx Pulldown to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Determines whether synthesizer is in PLL or bypass mode. Pulldown LVCMOS/LVTTL interface levels. Analog supply pin. Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. Core supply pin. Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input. Pulldown LVCMOS/LVTTL reference clock input. Selects between crystal or REF_CLK inputs as the the PLL Reference Pulldown source. Selects XTAL inputs when LOW. Selects REF_CLK when HIGH. LVCMOS/LVTTL interface levels. Negative supply pins. Differential output pair. LVPECL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 7 2, 20 3, 4 5 Name nc VCCO Q0, nQ0 MR
Unused Power Ouput Input
6 8 9, 11 10, 16 12, 13 14 15 17 18, 19
nPLL_SEL VCCA F_SEL0, F_SEL1 VCC XTAL_OUT, XTAL_IN REF_CLK nXTAL_SEL VEE nQ1, Q1
Input Power Input Power Input Input Input Power Output
NOTE: Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLDOWN Parameter Input Capacitance Input Pulldown Resistor Test Conditions Minimum Typical 4 51 Maximum Units pF k
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FEMTOCLOCKSTM CRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
4.6V -0.5V to VCC + 0.5V 50mA 100mA 73.2C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V10%, TA = -40C TO 85C
Symbol VCC VCCA VCCO IEE ICCA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 2.97 2.97 2.97 Typical 3.3 3.3 3.3 Maximum 3.63 3.63 3.63 130 13 Units V V V mA mA
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 2.5V5%, TA = -40C TO 85C
Symbol VCC VCCA VCCO IEE ICCA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 2.375 2.375 2.375 Typical 2.5 2.5 2.5 Maximum 2.625 2.625 2.625 115 12 Units V V V mA mA
TABLE 3C. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V10% OR 2.5V5%, TA = -40C TO 85C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current REF_CLK, MR, nPLL_SEL, nXTAL_SEL REF_CLK, MR, nPLL_SEL, nXTAL_SEL Test Conditions VCC = 3.3V VCC = 2.5V VCC = 3.3V VCC = 2.5V VCC = VIN = 3.63V or 2.625V VCC = VIN = 3.63V or 2.625V -5 Minimum Typical 2 1. 7 -0.3 -0.3 Maximum VCC + 0.3 VCC + 0.3 0.8 0.7 150 Units V V V V A A
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FEMTOCLOCKSTM CRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0.6 Typical Maximum VCCO - 0.9 VCCO - 1.7 1. 0 Units V V V
TABLE 3D. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V10% OR 2.5V5%, TA = -40C TO 85C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 to VCCO - 2V.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level NOTE: Characterized using an 18pF parallel resonant crystal. 22.4 Test Conditions Minimum Typical Maximum 25 27.2 50 7 1 Units MHz pF mW Fundamental
TABLE 5A. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V10%, TA = -40C TO 85C
Symbol fOUT t sk(o) t jit(O) tR / tF Parameter Output Frequency Output Skew; NOTE 1, 2 156.25MHz, (1.875MHz - 20MHz) RMS Phase Jitter ; NOTE 2, 3 Output Rise/Fall Time 125MHz, (1.875MHz - 20MHz) 62.5MHz, (1.875MHz - 20MHz) 20% to 80% 350 0.55 0.60 0.70 650 52 Test Conditions F_SEL[1:0] = 00 F_SEL[1:0] = 01 F_SEL[1:0] = 10 Minimum 140 112 56 Typical Maximum 170 136 68 30 Units MHz MHz MHz ps ps ps ps ps %
odc Output Duty Cycle 48 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the output differential cross points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Measured using cr ystal input.
TABLE 5B. AC CHARACTERISTICS, VCC = VCCA = VCCO = 2.5V5%, TA = -40C TO 85C
Symbol fOUT tsk(o) t jit(O) tR / tF Parameter Output Frequency Output Skew; NOTE 1, 2 156.25MHz, (1.875MHz - 20MHz) RMS Phase Jitter; NOTE 2, 3 Output Rise/Fall Time 125MHz, (1.875MHz - 20MHz) 62.5MHz, (1.875MHz - 20MHz) 20% to 80% 350 48
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Test Conditions F_SEL[1:0] = 00 F_SEL[1:0] = 01 F_SEL[1:0] = 10
Minimum 140 112 56
Typical
Maximum 17 0 136 68 30
Units MHz MHz MHz ps ps ps ps
0.55 0.60 0.74 650 52
ps %
odc Output Duty Cycle For Notes, see Table 5A above.
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FEMTOCLOCKSTM CRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
AT
TYPICAL PHASE NOISE
0 -10 -20 -30 -40 -50
156.25MHZ @ 3.3V
10 Gigabit Ethernet Filter 156.25MHz
RMS Phase Noise Jitter 1.875MHz to 20MHz = 0.55ps (typical)
dBc Hz
-60 -70 -80 -90 -100
NOISE POWER
Raw Phase Noise Data
-110 -120 -130 -140 -150
-160 -170 -180 -190 100 1k
Phase Noise Result by adding 10 Gigabit Ethernet Filter to raw data
100k 1M 10M 100M
10k
OFFSET FREQUENCY (HZ)
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FEMTOCLOCKSTM CRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2V
2V
V CC , VCCA, VCCO
Qx
SCOPE
V CC , VCCA, VCCO
Qx
SCOPE
LVPECL
nQx
LVPECL
nQx
VEE
VEE
-1.3V 0.33V
-0.5V 0.125V
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
nQx Qx nQy Qy
tsk(o)
nQ0, nQ1 Q0,Q1
t PW
t
PERIOD
odc =
t PW t PERIOD
x 100%
OUTPUT SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
Phase Noise Plot
Noise Power
Phase Noise Mask
80% Clock Outputs
80% VSW I N G
20% tR tF
20%
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
843002AGI-01
OUTPUT RISE/FALL TIME
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FEMTOCLOCKSTM CRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843002I-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA.
3.3V or 2.5V VCC .01F VCCA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS843002I-01 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 25MHz 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_OUT C1 33p X1 18pF Parallel Crystal XTAL_IN C2 27p
ICS843002I-01
Figure 2. CRYSTAL INPUt INTERFACE
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FEMTOCLOCKSTM CRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS:
CRYSTAL INPUT: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. REF_CLK INPUT: For applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the REF_CLK to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50
125 125
FOUT
FIN
Zo = 50 FOUT FIN
Zo = 50 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
Zo = 50 84 84
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
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FEMTOCLOCKSTM CRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
close to ground level. The R3 in Figure 4B can be eliminated and the termination is shown in Figure 4C.
TERMINATION
FOR
2.5V LVPECL OUTPUT
Figure 4A and Figure 4B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCCO = 2.5V, the VCCO - 2V is very
2.5V 2.5V VCCO=2.5V R1 250 Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R2 62.5 R4 62.5 R3 250
2.5V VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
R3 18
FIGURE 4A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
FIGURE 4C. 2.5V LVPECL TERMINATION EXAMPLE
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FEMTOCLOCKSTM CRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
parallel resonant 26.5625MHz crystal is used. The C1=27pF and C2=33pF are recommended for frequency accuracy. For different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy.
3.3V VCCA
LAYOUT GUIDELINE
Figure 5A shows a schematic example of the ICS843002I-01. An example of LVEPCL termination is shown in this schematic. Additional LVPECL termination approaches are shown in the LVPECL Termination Application Note. In this example, an 18 pF
VCC R3 133 Zo = 50 Ohm C3 10uF C4 0.01u VCC VCCO C6 0.1u Zo = 50 Ohm 10 9 8 7 6 5 4 3 2 1 C7 0.1u U1 ICS843002I-01 R4 82.5 +
R5 133
R2 10
Logic Control Input Examples
VCC
Set Logic Input to '1'
RU1 1K
VCC
Set Logic Input to '0'
RU2 Not Install
VCC F_SEL0 VCCA nc nPLL_SEL MR nQ0 Q0 VCCO nc
R6 82.5
VCC=3.3V
F_SEL1 XTAL_OUT XTAL_IN REF_CLK nXTAL_SEL VCC VEE nQ1 Q1 VCCO
VCCO=3.3V
Zo = 50 Ohm + Zo = 50 Ohm VCCO C8 0.1u R7 50 R8 50 -
To Logic Input pins
RD1 Not Install RD2 1K
To Logic Input pins
C2 33pF
X1 25 MHz 18pF C1 27pF
VCC
11 12 13 14 15 16 17 18 19 20
R9 50 C9 0.1u
Optional Termination
ICS843002I-01
FIGURE 5A. ICS843002I-01 SCHEMATIC EXAMPLE
PC BOARD LAYOUT EXAMPLE
Figure 5B shows an example of ICS843002I-01 P.C. board layout. The crystal X1 footprint shown in this example allows installation of either surface mount HC49S or through-hole HC49 package. The footprints of other components in this example are listed in the Table 6. There should be at least one decoupling capacitor per power pin. The decoupling capacitors should be located as close as possible to the power pins. The layout assumes that the board has clean analog power ground plane.
TABLE 6. FOOTPRINT TABLE
Reference C1, C2 C3 C4, C5, C6, C7, C8 Size 0402 0805 0603
R2 0603 NOTE: Table 6, lists component sizes shown in this layout example.
FIGURE 5B. ICS843002I-01 PC BOARD LAYOUT EXAMPLE
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FEMTOCLOCKSTM CRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843002I-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843002I-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 10% = 3.63V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.63V * 130mA = 471.9mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.63V, with all outputs switching) = 471.9mW + 60mW = 531.9mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.532W * 66.6C/W = 120.4C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE JA FOR 20-PIN TSSOP, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5C/W 73.2C/W
200
98.0C/W 66.6C/W
500
88.0C/W 63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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3. Calculations and Equations.
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FEMTOCLOCKSTM CRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT RL 50 VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, VOUT = V
OH_MAX
=V
CCO_MAX
- 0.9V
(VCCO_MAX - VOH_MAX) = 0.9V * For logic low, VOUT = V (V
CCO_MAX
OL_MAX
=V
CCO_MAX
- 1.7V
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CCO_MAX
CCO_MAX
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
L
CCO_MAX
-V
OH_MAX
)=
[(2V - 0.9V)/50] * 0.9V = 19.8mW ))/R ] * (V
L
Pd_L = [(V
OL_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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FEMTOCLOCKSTM CRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE 8.
JAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0 200
98.0C/W 66.6C/W
500
88.0C/W 63.5C/W
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards
114.5C/W 73.2C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS843002I-01 is: 2955
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FEMTOCLOCKSTM CRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
20 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 9. PACKAGE DIMENSIONS
SYMBOL MIN N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 6.40 6.40 BASIC 4.50 20 1.20 0.15 1.05 0.30 0.20 6.60 Millimeters MAX
Reference Document: JEDEC Publication 95, MO-153 www.icst.com/products/hiperclocks.html
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FEMTOCLOCKSTM CRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
Marking Package 20 Lead TSSOP 20 Lead TSSOP 20 Lead "Lead-Free" TSSOP 20 Lead "Lead-Free" TSSOP Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
TABLE 10. ORDERING INFORMATION
Part/Order Number ICS843002AGI-01 ICS843002AGI-01T ICS843002AGI-01LF ICS843002AGI-01LFT ICS43002AI01 ICS43002AI01 ICS3002AI01L ICS3002AI01L
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843002AGI-01
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